hw:fpga:virtex5fxt:start
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hw:fpga:virtex5fxt:start [2009/05/30 09:06] szymon.kulis |
hw:fpga:virtex5fxt:start [2019/03/08 14:08] (current) |
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| ====== Xilinx Virtex-5 FXT Evaluation Kit ====== | ====== Xilinx Virtex-5 FXT Evaluation Kit ====== | ||
| + | * [[http://www.em.avnet.com/evk/home/0,4534,CID%253D46471%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526BID%253DDF2%2526CTP%253DEVK,00.html?SUL=virtex5fxt-evl | Eval board description on Avnet page ]] | ||
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| The Xilinx Virtex-5 FXT Evaluation Kit provides the necessary features for exploring PowerPC 440 based system architectures using the Xilinx Virtex-5 FXT FPGA family. This low cost evaluation platform is ideal for both software and FPGA designers needing an easy to use, entry level system for code development and debug, processor systems prototyping, and general FXT evaluation. | The Xilinx Virtex-5 FXT Evaluation Kit provides the necessary features for exploring PowerPC 440 based system architectures using the Xilinx Virtex-5 FXT FPGA family. This low cost evaluation platform is ideal for both software and FPGA designers needing an easy to use, entry level system for code development and debug, processor systems prototyping, and general FXT evaluation. | ||
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| * Image processing | * Image processing | ||
| - | + | === Foto=== | |
| - | * [[http://www.em.avnet.com/evk/home/0,4534,CID%253D46471%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526BID%253DDF2%2526CTP%253DEVK,00.html?SUL=virtex5fxt-evl | Eval board description on Avnet page ]] | + | {{ :hw:fpga:virtex5fxt:xlx-drc-virtex5fxt-evl.jpg }} |
| + | * {{:hw:fpga:virtex5fxt:v5fxt_block_diagram_021108.pdf|Xilinx Virtex-5 FXT Evaluation Kit - Block Diagram}} | ||
| + | * {{:hw:fpga:virtex5fxt:xlx_v5fxt_evl-pb052208f.pdf|Xilinx Virtex-5 FXT Evaluation Kit - Product Brief}} | ||
| + | * {{:hw:fpga:virtex5fxt:exp_specification_v1_4.pdf|EXP Expansion Connector Specification}} | ||
| ==== App Notes/Ref Designs ==== | ==== App Notes/Ref Designs ==== | ||
| Line 62: | Line 67: | ||
| + | ==== Other Xilinx app notes ==== | ||
| + | * {{:hw:fpga:virtex5fxt:ug198.pdf| Virtex-5 FPGA RocketIO GTX Transceiver User Guide (ug198) }} | ||
| + | * {{:hw:fpga:virtex5fxt:p105-107_57-bellinix.pdf| Selecting a High-Speed POL Converter for FPGAs }} | ||
| + | * {{:hw:fpga:virtex5fxt:serialio-book.pdf|High-Speed Serial I/O Made Simple}} | ||
| + | ==== Prom INFO ==== | ||
| + | * 28F128P30 | ||
| + | * 16 M | ||
| + | * 16 bit | ||
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