Initial Vivado design – only Zynq + single AXI GPIO

1. Open AXI GPIO properties (double click on block), go to IP Configuration tab and enable Enable Interrupt on bottom
2. Open Zynq Processing System, go to Interrupts tab, enable and unfold Fabric Interrupts,
   unfold PL-PS Interrupt Port and enable IRQ_F2P[15:0]
3. Draw connection from ip2intc_irpt port at AXI GPIO to IRQ_F2P[0:0] port at Zynq Processing System
4. Validate design
5. Go to Sources tab in Vivado and select Create HDL Wrapper for top cell
6. Generate bitstream
7. After done, select File→Export→Export Hardware and make sure that Include Bitstream is checked