
###################
#   Variables     #
###################

VVP = vvp/lo_controlLogic-test.vvp\
	  vvp/lo_dataReadout-test.vvp\
	  vvp/lo_commandDecoder-cmds-test.vvp\
	  vvp/lo_commandDecoder-addr-test.vvp\
	  vvp/lo_calibPulseTrain-one-test.vvp\
      vvp/lo_calibPulseTrain-100-test.vvp\
      vvp/lo_calibPulseTrain-500-test.vvp\
	  vvp/lo_loadOrClear-test.vvp\
	  vvp/lo_254clkImp-test.vvp\
	  vvp/lo_126clkImp-test.vvp\
	  vvp/lo_12shiftRegAddr-test.vvp\
	  vvp/lo_2shiftRegMem-test.vvp\
	  vvp/lo_catch1to0tran-test.vvp\
	  vvp/lo_1clkBImp-test.vvp\
	  vvp/lo_wait3clkRep-test.vvp\
	  vvp/lo_wait3clk-test.vvp\
	  vvp/lo_3clkImpRep-test.vvp\
      vvp/lo_3clkImp-test.vvp

LOG := $(patsubst vvp/%.vvp, log/%.log, $(VVP))

VCD := $(patsubst log/%.log, vcd/%.vcd, $(LOG))

DIFF := $(patsubst log/%.log, diff/%.diff, $(LOG))

###################
#   Global Rules  #
###################

.PHONY: all clean cleanvvp cleanvcd

all: $(LOG) topModule.v

clean: cleanvvp cleanvcd
	rm -f $(LOG)

cleanvvp:
	rm -f $(VVP)

cleanvcd:
	rm -f $(VCD)


##################
#   DIFF FILES   #
##################


$(allDIFF): diff/%.diff: log/%.log 
	diff $< $(patsubst log/%.log, logModel/%.log, $<) > $@


#################
#   LOG FILES   #
#################

$(LOG): log/%.log: vvp/%.vvp 
	vvp $< > $@

#################
#   Top Module  #
#################
topModule.v: modules/lo_controlLogic.v \
	modules/lo_12shiftRegAddr.v modules/lo_2shiftRegMem.v \
	modules/lo_2shiftRegStrobe.v modules/lo_3clkImp.v \
	modules/lo_calibPulseTrain.v modules/lo_commandDecoder.v \
	modules/lo_dataReadout.v modules/lo_del1clk.v modules/lo_loadOrClear.v \
	modules/lo_parMem.v modules/lo_rs.v modules/lo_254clkImp.v \
	modules/lo_catch1to0tran.v modules/lo_parCounter.v \
	modules/lo_readDataSeq.v modules/lo_wait3clk.v modules/lo_4clkReset.v
	cat $^ > $@
	iverilog -S -tnull -Wall $@ 


#################
#   VVP  FILES  #
#################
vvp/lo_controlLogic-test.vvp: tests/lo_controlLogic-test.v \
    otherMods/sid_commandGenerator.v modules/lo_controlLogic.v \
	modules/lo_12shiftRegAddr.v modules/lo_2shiftRegMem.v \
	modules/lo_2shiftRegStrobe.v modules/lo_3clkImp.v \
	modules/lo_calibPulseTrain.v modules/lo_commandDecoder.v \
	modules/lo_dataReadout.v modules/lo_del1clk.v modules/lo_loadOrClear.v \
	modules/lo_parMem.v modules/lo_rs.v modules/lo_254clkImp.v \
	modules/lo_catch1to0tran.v modules/lo_parCounter.v \
	modules/lo_readDataSeq.v modules/lo_wait3clk.v modules/lo_4clkReset.v
	iverilog -Wall -o $@ $^

vvp/lo_dataReadout-test.vvp: tests/lo_dataReadout-test.v \
	modules/lo_dataReadout.v modules/lo_readDataSeq.v \
	modules/lo_parCounter.v modules/lo_rs.v modules/lo_3clkImp.v
	iverilog -Wall -o $@ $^

vvp/lo_commandDecoder-cmds-test.vvp: tests/lo_commandDecoder-cmds-test.v \
	modules/lo_commandDecoder.v otherMods/sid_commandGenerator.v
	iverilog -Wall -o $@ $^

vvp/lo_commandDecoder-addr-test.vvp: tests/lo_commandDecoder-addr-test.v \
	modules/lo_commandDecoder.v otherMods/sid_commandGenerator.v
	iverilog -Wall -o $@ $^

vvp/lo_calibPulseTrain-one-test.vvp: tests/lo_calibPulseTrain-one-test.v\
	modules/lo_calibPulseTrain.v modules/lo_parCounter.v \
	modules/lo_254clkImp.v modules/lo_catch1to0tran.v modules/lo_del1clk.v
	iverilog -Wall -o $@ $^

vvp/lo_calibPulseTrain-100-test.vvp: tests/lo_calibPulseTrain-100-test.v\
	modules/lo_calibPulseTrain.v modules/lo_parCounter.v \
	modules/lo_254clkImp.v modules/lo_catch1to0tran.v modules/lo_del1clk.v
	iverilog -Wall -o $@ $^

vvp/lo_calibPulseTrain-500-test.vvp: tests/lo_calibPulseTrain-500-test.v\
	modules/lo_calibPulseTrain.v modules/lo_parCounter.v \
	modules/lo_254clkImp.v modules/lo_catch1to0tran.v modules/lo_del1clk.v
	iverilog -Wall -o $@ $^

vvp/lo_loadOrClear-test.vvp: tests/lo_loadOrClear-test.v \
	modules/lo_loadOrClear.v modules/lo_rs.v modules/lo_wait3clk.v \
	modules/lo_3clkImp.v modules/lo_catch1to0tran.v modules/lo_del1clk.v
	iverilog -Wall -o $@ $^

vvp/lo_254clkImp-test.vvp: tests/lo_254clkImp-test.v modules/lo_254clkImp.v
	iverilog -Wall -o $@ $^

vvp/lo_126clkImp-test.vvp: tests/lo_126clkImp-test.v modules/lo_126clkImp.v
	iverilog -Wall -o $@ $^

vvp/lo_12shiftRegAddr-test.vvp: tests/lo_12shiftRegAddr-test.v \
	modules/lo_12shiftRegAddr.v modules/lo_catch1to0tran.v modules/lo_3clkImp.v
	iverilog -Wall -o $@ $^

vvp/lo_2shiftRegMem-test.vvp: tests/lo_2shiftRegMem-test.v \
	modules/lo_2shiftRegMem.v
	iverilog -Wall -o $@ $^

vvp/lo_catch1to0tran-test.vvp: tests/lo_catch1to0tran-test.v \
	modules/lo_catch1to0tran.v
	iverilog -Wall -o $@ $^

vvp/lo_1clkBImp-test.vvp: tests/lo_1clkBImp-test.v modules/lo_1clkBImp.v
	iverilog -Wall -o $@ $^

vvp/lo_wait3clkRep-test.vvp: tests/lo_wait3clkRep-test.v \
	modules/lo_wait3clkRep.v
	iverilog -Wall -o $@ $^

vvp/lo_wait3clk-test.vvp: tests/lo_wait3clk-test.v modules/lo_wait3clk.v
	iverilog -Wall -o $@ $^

vvp/lo_3clkImpRep-test.vvp: tests/lo_3clkImpRep-test.v modules/lo_3clkImpRep.v
	iverilog -Wall -o $@ $^

vvp/lo_3clkImp-test.vvp: tests/lo_3clkImp-test.v modules/lo_3clkImp.v
	iverilog -Wall -o $@ $^

