EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK indicates Clock ports, (SIGIS = CLK) INTR indicates Interrupt ports,(SIGIS = INTR) RESET indicates Reset ports, (SIGIS = RST) BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# | NAME | DIR | [LSB:MSB] | SIG | ATTRIBUTES
0 GLB | fpga_0_FLASH_8Mx16_adv_dummy_pin | O | 1 | net_gnd |
1 GLB | fpga_0_FLASH_8Mx16_byte_dummy_pin | O | 1 | net_vcc |
2 GLB | fpga_0_FLASH_8Mx16_clk_dummy_pin | O | 1 | net_vcc |
3 GLB | fpga_0_FLASH_8Mx16_rpn_dummy_pin | O | 1 | net_vcc |
4 GLB | fpga_0_FLASH_8Mx16_wait_dummy_pin | O | 1 | net_gnd |
5 A | fpga_0_FLASH_8Mx16_Mem_DQ_pin | IO | 0:15 | fpga_0_FLASH_8Mx16_Mem_DQ |
6 A | fpga_0_FLASH_8Mx16_Mem_CEN_pin | O | 0:0 | fpga_0_FLASH_8Mx16_Mem_CEN |
7 A | fpga_0_FLASH_8Mx16_Mem_OEN_pin | O | 0:0 | fpga_0_FLASH_8Mx16_Mem_OEN |
8 A | fpga_0_FLASH_8Mx16_Mem_WEN_pin | O | 1 | fpga_0_FLASH_8Mx16_Mem_WEN |
9 B | fpga_0_FLASH_8Mx16_Mem_A_pin | O | 7:31 | fpga_0_FLASH_8Mx16_Mem_A |
10 C | fpga_0_RS232_RX_pin | I | 1 | fpga_0_RS232_RX |
11 C | fpga_0_RS232_TX_pin | O | 1 | fpga_0_RS232_TX |
12 D | sys_clk_pin | I | 1 | dcm_clk_s | CLK
13 E | sys_rst_pin | I | 1 | sys_rst_s | RESET