EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK indicates Clock ports, (SIGIS = CLK) INTR indicates Interrupt ports,(SIGIS = INTR) RESET indicates Reset ports, (SIGIS = RST) BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# | NAME | DIR | [LSB:MSB] | SIG | ATTRIBUTES
0 GLB | fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin | O | 1 | net_vcc |
1 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ | IO | 31:0 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ |
2 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS | IO | 3:0 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS |
3 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N | IO | 3:0 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N |
4 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin | O | 12:0 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_A |
5 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin | O | 1:0 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA |
6 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin | O | 1 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N |
7 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin | O | 1 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE |
8 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin | O | 1:0 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N |
9 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin | O | 1:0 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK |
10 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin | O | 1 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N |
11 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin | O | 3:0 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM |
12 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin | O | 0:0 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT |
13 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin | O | 1 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N |
14 A | fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin | O | 1 | fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N |
15 B | fpga_0_DIP_Switches_8Bit_GPIO_in_pin | I | 0:7 | fpga_0_DIP_Switches_8Bit_GPIO_in |
16 C | fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin | I | 7:0 | fpga_0_Hard_Ethernet_MAC_GMII_RXD_0 |  |  | # | NAME | DIR | [LSB:MSB] | SIG | ATTRIBUTES
17 C | fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin | I | 1 | fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0 |
18 C | fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin | I | 1 | fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0 |
19 C | fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin | I | 1 | fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0 |
20 C | fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin | I | 1 | fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0 |
21 C | gbe_mclk | I | 1 | gtx_clk | CLK
22 C | fpga_0_Hard_Ethernet_MAC_MDIO_0_pin | IO | 1 | fpga_0_Hard_Ethernet_MAC_MDIO_0 |
23 C | fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin | O | 7:0 | fpga_0_Hard_Ethernet_MAC_GMII_TXD_0 |
24 C | fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin | O | 1 | fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0 |
25 C | fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin | O | 1 | fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0 |
26 C | fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin | O | 1 | fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0 |
27 C | fpga_0_Hard_Ethernet_MAC_MDC_0_pin | O | 1 | fpga_0_Hard_Ethernet_MAC_MDC_0 |
28 C | fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin | O | 1 | fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n |
29 D | fpga_0_LEDs_8Bit_GPIO_d_out_pin | O | 0:7 | fpga_0_LEDs_8Bit_GPIO_d_out |
30 E | fpga_0_RS232_RX_pin | I | 1 | fpga_0_RS232_RX |
31 E | fpga_0_RS232_TX_pin | O | 1 | fpga_0_RS232_TX |
32 F | sys_clk_pin | I | 1 | dcm_clk_s | CLK
33 G | sys_rst_pin | I | 1 | sys_rst_s | RESET